1. Field of the Invention
The present invention relates to a semiconductor circuit, and particularly to a semiconductor circuit used in CATV (CAble TeleVision) hybrid IC (HIC).
2. Description of the Related Art
In HIC (hybrid IC) broadband amplifiers for CATV, a plurality of stages of amplifiers are connected in series via coaxial cable, and a desired gain slope must be established across the entire employed frequency band to correct for characteristic lost in the coaxial cable. Gain slope is such that gain increases with higher frequencies within the bandwidth.
Realization of desired gain slope in the frequency bands employed has become more difficult in recent years as the frequency bandwidths that are used have extended to higher frequencies.
FIG. 1 and FIG. 2 are circuit diagrams showing the configuration of circuits for realizing a desired gain slope used in the prior art as disclosed in Japanese Utility Model laid-open application No. 85810/83.
In the circuits shown in FIG. 1 and FIG. 2, a parallel resonant circuit is formed by inductor L101, which is provided in a bias feedback circuit, and capacitor C102, which is provided between the base and emitter of transistor Tr 101. In addition, damping resistor R106 connected in a series with capacitor C102 between the base and emitter of transistor Tr101 is provided to control Q in the resonant circuit.
In a circuit configured according to the foregoing description, the resonance frequency is altered by changing the element constants of inductor L101 and capacitor C102, thereby regulating the peaking frequency.
FIG. 3 and FIG. 4 are circuit diagrams showing the configuration of circuits for realizing a desired gain slope used in the prior art as disclosed in Japanese Patent Laid-open No. 264404/89.
In the circuit shown in FIG. 3, a serial resonant circuit is formed by capacitor C112 and inductor L111 in an interstage circuit provided between two amplifier circuits, and in the circuit shown in FIG. 4, FET(Field Effect Transistor) Tr113 is provided such that inductor L111 is connected in parallel between the source and drain, and a parallel resonant circuit is formed by inductor L111 and the capacitance between the source and drain of FET Tr113.
In the circuits configured according to the foregoing description, alteration of resonance frequency is realized by changing the gate bias to vary the capacitance between the source and drain of FET Tr113, thereby regulating peaking frequency.
However, the above-described circuits of the prior art have the following drawbacks:
(1) In the circuits shown in FIG. 1 and FIG. 2, resonance frequency is altered by changing the element constants of inductor L101 and capacitor C102 to regulate the peaking frequency, but the impedance on the input side and output side change according to the amount of peaking because inductor L101 and capacitor C102 are provided in the feedback circuit. PA1 (2) In the circuits shown in FIG. 3 and FIG. 4, the resonance frequency is changed and the peaking frequency adjusted by changing the gate bias to change capacitance between the source and drain of the FET, and these circuits therefore require a variable bias to allow change of the gate bias. These circuits also require the additional provision of a FET. As a result both the scale and cost of the circuit increases.
The resulting circuit therefore has the three factors of input and output impedance and gain slope, and design and adjustment consequently require considerable time and trouble.
In the circuit shown in FIG. 3, moreover, capacitor C111 and inductor L111 between active elements must also be changed to alter the resonance frequency, and mismatching between elements having gain tends to cause problems in characteristics such as oscillation and instability.